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A26E001A
2M and 256K MaskRAM
Document Title 2M and 256K MaskRAM Revision History
Rev. No.
2.0 2.1
History
Final spec release Change tOE speed from 150ns to 200ns
Issue Date
October 12, 1998 November 20, 1998
Remark
Final
(November, 1998, Version 2.1)
AMIC Technology, Inc.
A26E001A
2M and 256K MaskRAM
Features
n Power supply range: 1.8V to 3.3V n Access time: 450 ns (max.) n Current: Low power version: Operating: 4mA (max.) Standby: 10A (max.) n Extended operating temperature range: -25 to 85 C C n n n n n Full static operation, no clock or refreshing required All inputs and outputs are CMOS compatible Common I/O using three-state output Data retention voltage: 1.6V (min.) Available in 32-pin TSOP and sTSOP packages
General Description
The A26E001A is a low operating current 262,144 x 8 bit CMOS MASK ROM and 32,768 x 8 bit CMOS SRAM integrated into one chip. It operates on a low power supply voltage from 1.8V to 3.3V, with two chip selects to enable the MASK ROM or SRAM independently. Inputs and three-state outputs are CMOS compatible and allow for direct interfacing with common system bus structures. Minimum standby power is drawn by this device when ROMCE and RAMCE are at a high level, independent of the other input levels. Data retention is guaranteed at a power supply voltage as low as 1.6V.
Pin Configuration
Pin Description
~ ~
~ ~
A11 A9 A8 A13 A14 A17 RAMCE VCC WE A16 A15 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
A26E001AV
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
OE A10 ROMCE D7 D6 D5 D4 D3 GND D2 D1 D0 A0 A1 A2 A3
Pin No. 1 - 6, 10 - 20, 31 7 9 21 - 23, 25 - 29 30
Symbol A0 - A17
RAMCE
Description Address Inputs SRAM Enable Write Enable Data Input/Outputs ROM Enable Output Enable Power Supply Ground
WE
D0 - D7
ROMCE
~ ~
A11 A9 A8 A13 A14 A17 RAMCE VCC WE A16 A15 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
~ ~
A26E001AX
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
OE A10 ROMCE D7 D6 D5 D4 D3 GND D2 D1 D0 A0 A1 A2 A3
32 8 24
OE
VCC GND
(November, 1998, Version 21)
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AMIC Technology, Inc.
A26E001A
Block Diagram
VCC GND A0 - A14 A0-A14 A15 - A17 ADDRESS BUFFER
RAM
WE OE RAMCE
D0-D7 D0 - D7 DATA BUFFER CIRCUIT D0-D7 WE A0-A14 OE ROMCE A15-A17 WE OE RAMCE ROMCE CONTROL CIRCUIT
ROM
Truth Table
Mode Standby Output Disable ROM Read Output Disable SRAM Read SRAM Write
ROMCE RAMCE OE WE
D0 - D7 High Z High Z DOUT High Z DOUT DIN
Supply Current ISB, ISB1 ICCR ICCR ICCS ICCS ICCS
H L L H H H
H H H L L L
X H L H L X
X X X H H L
Notes: 1. X = H or L 2. A15 - A17 are only valid for ROM. 3. In case that ROMCE and RAMCE are "L" at the same time, both ROM and SRAM will be disabled.
(November, 1998, Version 2.1)
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AMIC Technology, Inc.
A26E001A
Recommended DC Operating Conditions
Symbol VCC GND VIH VIL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 1.8 0 VCC x 0.7 -0.3 Typ. 3.0 0 Max. 3.3 0 VCC + 0.3 VCC x 0.3 (TA = -25 to + 85 C C) Unit V V V V
Absolute Maximum Ratings*
VCC to GND . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +4.6V IN, IN/OUT Volt to GND . . . . . . . . . . -0.5V to VCC + 0.5V Operating Temperature, Topr . . . . . . . . . -25 to +85 C C Storage Temperature, Tstg . . . . . . . . . . -55 to +125 C C Power Dissipation, PT . . . . . . . . . . . . . . . . . . . . . . . 0.7W Soldering Temp. & Time . . . . . . . . . . . . . . 260 10 sec C,
*Comments
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. (TA = -25 to + 85 VCC = 1.8V to 3.3V) C C, Min. Max. 1 1 Unit A A Conditions VIN = GND to VCC VI/O = GND to VCC Min. Cycle, Duty = 100% ROMCE = VIL and RAMCE = VIH, II/O = 0mA, VIN = VCC or GND Min. Cycle, Duty = 100% ROMCE = VIH and RAMCE = VIL, II/O = 0mA, VIN = VCC or GND
ROMCE = VIH and RAMCE = VIH ROMCE VCC - 0.2V and RAMCE VCC - o.2V
DC Electrical Characteristics
Symbol ILI ILO Parameter Input Leakage Current Output Leakage Current
ICCR
ROM Operating Current
-
4
mA
ICCS
SRAM Operating Current
-
4
mA
ISB Standby Supply Current
-
50
A A
ISB1
-
10
VOL VOH
Output Low Voltage Output High Voltage
VCC - 0.4
0.4 -
V V
IOL = 200A IOH = -200A
(November, 1998, Version 2.1)
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AMIC Technology, Inc.
A26E001A
Capacitance
Symbol CI* CO* Parameter Input Capacitance Input/Output Capacitance Min. Max. 6 8 Unit pF pF (TA = 25 f = 1.0MHz) C, Conditions TA = 25 C f = 1.0MHz
* These parameters are sampled and not 100% tested.
AC Characteristics (ROM/SRAM Selection)
Symbol tRTS tSTR Parameter
ROMCE Disable to RAMCE Enable Time RAMCE Disable to ROMCE Enable Time
(TA = -25 to +85 VCC = 1.8V to 3.3V) C C, Min. 10 10 Max. Unit ns ns
AC Characteristics (ROM Selected)
Symbol tRC tAA tACE tOE tCLZ tOLZ tCHZ tOHZ tOH Notes: Read Cycle Time Address Access Time
ROMCE Chip Enable Access Time
(TA = -25 to +85 VCC = 1.8V to 3.3V) C C, Min. 500 10 10 10 Max. 450 450 200 100 100 Unit ns ns ns ns ns ns ns ns ns
Parameter
Output Enable to Output Valid
ROMCE Chip Enable to Output in Low Z
Output Enable to Output in Low Z
ROMCE Chip Disable to Output in High Z
Output Disable to Output in High Z Output Hold from Address Change
tCHZ, and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels.
(November, 1998, Version 2.1)
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AMIC Technology, Inc.
A26E001A
AC Characteristics (SRAM Selected)
Symbol Read Cycle tRC tAA tACE tOE tCLZ tOLZ tCHZ tOHZ tOH Write Cycle tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOW Notes: Write Cycle Time
RAMCE Chip Enable to End of Write
(TA = -25 to +85 VCC = 1.8V to 3.3V) C C, Min. Max. Unit
Parameter
Read Cycle Time Address Access Time
RAMCE Chip Enable Access Time
500 10 10 10
450 450 200 100 100 -
ns ns ns ns ns ns ns ns ns
Output Enable to Output Valid
RAMCE Chip Enable to Output in Low Z
Output Enable to Output in Low Z
RAMCE Chip Disable to Output in High Z
Output Disable to Output in High Z Output Hold from Address Change
500 220 0 220 200 0 100 0 10
100 -
ns ns ns ns ns ns ns ns ns ns
Address Setup Time Address Valid to End of Write Write Pulse Width Write Recovery Time Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time Output Active from End of Write
tCHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels.
(November, 1998, Version 2.1)
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AMIC Technology, Inc.
A26E001A
Timing Waveforms (ROM/SRAM Selection)
ROMCE tRTS tSTR
RAMCE
Timing Waveforms (ROM Selected)
Read from Address ( ROMCE = Active, OE = Active)
tRC ADDRESS INPUTS
tAA
tOH
DATA OUT
Read from ROMCE Chip Enable or Output Enable (Address Valid)
tACE ROMCE tCHZ tOE
OE
tOLZ
tOHZ
DATA OUT tCLZ
(November, 1998, Version 2.1)
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AMIC Technology, Inc.
A26E001A
Timing Waveforms (SRAM Selected)
Read Cycle 1 (1)
tRC Address
tAA
OE
tOE tOLZ 5 RAMCE
tOH
tACE tCLZ 5 DOUT
tOHZ 5 tCHZ 5
Read Cycle 2 (1, 2, 4)
tRC Address
tAA tOH tOH
DOUT
(November, 1998, Version 2.1)
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AMIC Technology, Inc.
A26E001A
Timing Waveforms (SRAM Selected continued)
Read Cycle 3 (1, 3, 4)
RAMCE
tACE tCLZ 5
tCHZ 5
DOUT
Notes: 1. WE is high for Read Cycle. 2. Device is continuously enabled, RAMCE = VIL. 3. Address valid prior to or coincident with RAMCE transition low. 4. OE = VIL. 5. Transition is measured 500mV from steady state. This parameter is sampled and not 100% tested. Write Cycle 1(6) (Write Enable Controlled)
tWC Address tAW tCW 5 RAMCE (4) tWR 3
tAS1
tWP 2
WE
tDW
tDH
DIN tWHZ 7 tOW 7 DOUT
(November, 1998, Version 2.1)
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AMIC Technology, Inc.
A26E001A
Timing Waveforms (SRAM Selected continued)
Write Cycle 2 (6) (Chip Enable Controlled)
tWC Address tAW tCW RAMCE tAS1 (4)
5
tWR 3
tWP 2 WE
tDW
tDH
DIN
tWHZ 7
DOUT
Notes: 1. 2. 3. 4.
tAS is measured from the address valid to the beginning of Write. A Write occurs during the overlap (tWP) of a low RAMCE and a low WE . tWR is measured from the earliest of RAMCE or WE going high to the end of the Write cycle. If the RAMCE low transition occurs simultaneously with the WE low transition or after the WE transition, outputs remain in a high impedance state. 5. tCW is measured from the later of RAMCE going low to the end of Write. 6. OE level is high or low. 7. Transition is measured 500mV from steady state. This parameter is sampled and not 100% tested.
(November, 1998, Version 2.1)
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AMIC Technology, Inc.
A26E001A
AC Test Conditions
Input Pulse Levels Input Rise And Fall Time Input and Output Timing Reference Levels Output Load 0V, VCC 3 ns VCC/2 See Figure 1
CL 30pF
* Including scope and jig.
Figure 1. Output Load
Data Retention Characteristics (TA = -25 to 85 C C)
Symbol VDR Parameter VCC for Data Retention Min. 1.6 Max. 3.6 Unit V Conditions
RAMCE VCC - 0.2V
ICCDR
Data Retention Current
-
3
A
VCC = 1.6V, RAMCE VCC - 0.2V VIN 0V See Retention Waveform
tCDR tR
Chip Disable to Data Retention Time Operation Recovery Time
0 tRC
-
ns ns
Low VCC Data Retention Waveform
DATA RETENTION MODE VCC 3.0V tCDR VDR 1.6V 3.0V tR
RAMCE
VIH RAMCE VDR - 0.2V
VIH
(November, 1998, Version 2.1)
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AMIC Technology, Inc.
A26E001A
Ordering Information
Part No. A26E001AV A26E001AX Access Time (ns) 450 450 Operation Current Max. (mA) 4 4 Standby Current Max. (A) 10 10 Package 32L TSOP 32L sTSOP
(November, 1998, Version 2.1)
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AMIC Technology, Inc.
A26E001A
Package Information TSOP 32L TYPE I (8 X 20mm) Outline Dimensions
D
unit: inches/mm
e
A2
E
A1
c
L LE
HD Detail "A"
Detail "A"
y
D
S
b
Dimensions in inches Symbol A A1 A2 b c D E e HD L LE S y 0.779 0.016 0 Min 0.002 0.037 0.007 0.004 0.720 Nom 0.039 0.009 0.724 0.315 0.020 BSC 0.787 0.020 0.032 0.795 0.024 0.020 0.003 5 Max 0.047 0.006 0.041 0.011 0.008 0.728 0.319
Dimensions in mm Min 0.05 0.95 0.18 0.11 18.30 Nom 1.00 0.22 18.40 8.00 0.50 BSC 19.80 0.40 0 20.00 0.50 0.80 20.20 0.60 0.50 0.08 5 Max 1.20 0.15 1.05 0.27 0.20 18.50 8.10
Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension S includes end flash.
(November, 1998, Version 2.1)
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AMIC Technology, Inc.
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A26E001A
Package Information sTSOP 32L TYPE I (8 X 13.4mm) Outline Dimensions
unit: inches/mm
e
A2
E
A1
c
L LE Detail "A"
D1 D Detail "A"
D
0.076MM
S
SEATING PLANE
b
Dimensions in inches Symbol A A1 A2 b c E e D D1 L LE S 0 0.520 0.461 0.012 0.0275 Min 0.002 0.037 0.007 0.0056 0.311 Nom 0.039 0.008 0.0059 0.315 0.020 TYP 0.528 0.465 0.020 0.0315 0.0109 TYP 3 5 0.535 0.469 0.028 0.0355 Max 0.049 0.041 0.009 0.0062 0.319
Dimensions in mm Min 0.05 0.95 0.17 0.142 7.90 Nom 1.00 0.20 0.150 8.00 0.50 TYP 13.20 11.70 0.30 0.700 13.40 11.80 0.50 0.800 0.278 TYP 0 3 5 13.60 11.90 0.70 0.900 Max 1.25 1.05 0.23 0.158 8.10
Notes: 1. The maximum value of dimension D1 includes end flash. 2. Dimension E does not include resin fins. 3. Dimension S includes end flash.
(November, 1998, Version 2.1)
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AMIC Technology, Inc.
A

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